The present invention relates to a method of manufacturing a semiconductor device having fine contacts.
In recent semiconductor devices, as the element density and degree of integration, increase the wirings and contact portions are becoming finer and finer. The conventional method of forming a contact structure is described in detail below while referring to the process sectional views shown in FIGS. 5(a) to (f).
First, employing a known technology on one principal plane of a silicon substrate 1, a selective oxidation (LOCOS) film 2 for separation of elements is formed in a specified region at a thickness of about 500 nm. Consequently, a gate oxide film 3 of 20 nm in thickness is formed on the principal plane of the silicon substrate 1. Next, a polycrystalline silicon gate layer 4a of 300 to 500 nm in thickness and polycrystalline silicon wiring layer 4b are formed on the gate oxide film 3 and the oxidation film 2 respectively. Afterwards using the polycrystalline silicon gate layer 4a as a mask, ions are implanted to form a diffusion region (diffusion region wiring) 5, and ions are activated by annealing, thereby forming a MOS type semiconductor device. In succession, an oxide film 6 of about 300 nm in thickness is deposited on the entire area of the substrate surface [FIG. 5(a)]. The oxide film 6 is generally formed by the chemical vapor deposition (CVD) method.
On the oxide film 6, a BPSG film 7 of 400 nm in thickness is deposited by using CVD. The BPSG film 7 has impurity concentrations of, for example, 3 wt. % of boron (B) and 5 wt. % of phosphorus (P), approximately.
In a nitrogen atmosphere subsequently, heat treatment is applied for 60 minutes at 900.degree. C. to cause the BPSG film 7 to flow in order to lessen the step difference of the surface of the BPSG film [FIG. 5(b)]. At this time, the oxide film 6 prevents thermal diffusion of phosphorus (P) and boron (B) from the BPSG film 7 to the silicon substrate 1.
On the BPSG film 7, a photoresist (not shown) is applied, a specified resist pattern is formed by photoetching, and using this resist pattern as a mask, the oxide film 6 and BPSG film 7 are removed by etching, thereby forming a contact hole 8. Furthermore, the resist pattern is removed [FIG. 5(c)].
Then, a polycide wiring layer 9 is formed on the BPSG film 7 and in the contact hole 8 [FIG. 5(d)]. This polycide wiring layer 9 is composed of two layers, that is, a lower layer of a 200 nm thick polycrystalline silicon film 9a and the upper layer of a 200 nm thick tungsten silicide (WiSix) film 9b. Since phosphorus is to be introduced into the polycrystalline silicon film 9a, it is heat-treated in a nitrogen atmosphere containing a phosphorus compound, and the tungsten silicide film 9b is deposited by using CVD. This polycide wiring layer 9 is patterned by anisotropic etching, such as RIE.
This polycide wiring layer 9 has a lower wiring resistance than the single layer of polycrystalline silicon, so that the circuit delay due to the wiring resistance may be improved.
Then, on the entire area of the substrate surface, as shown in FIG. 5(e), a BPSG film 10 is deposited at a thickness of 500 nm. The BPSG film 10 has impurity concentrations of, for example, 3 wt. % of boron (B) and 5 wt. % of phosphorus (P), approximately.
Afterwards, in a nitrogen atmosphere, heat treatment is performed for 60 minutes at 900.degree. C. to flow cause the BPSG film 10 to flow, thereby lessening the step difference due to the polycrystalline silicon gate layer 4a, 4b and the polycide wiring layer 9.
Then, on the BPSG film 10, a photoresist (not shown) is applied, and a specified resist pattern is formed by photoetching. In consequence, using the resist pattern as the a mask, the oxide film 6 and BPSG films 7, 10 are removed by RIE etching, and thereby, contact holes 11 are formed [FIG. 5(e)]. Then, the resist pattern is removed.
Next, a wiring layer 12 of an aluminum alloy is formed. The aluminum alloy wiring layer 12 is deposited at a film thickness of 0.8 .mu.m by a known method such as sputtering, and is patterned by anisotropic etching such as RIE etching [FIG. 5(f)].
After these steps, the semiconductor device of the prior art is nearly complete.
However, when the contact holes 11 must be formed in a fine pattern, the aspect ratio (hole depth/hole width) of the contact holes 11 becomes high, exceeding 1. As a result, the portion of the aluminum alloy film 12 formed on the side wall of the contact hole 11 becomes thin, and the resistance of the aluminum alloy film 12 may increase, the reliability of the aluminum alloy film 12 may be lessened (for example, electromigration may be likely to occur) and other defects may take place. Thus, in the conventional method of manufacturing a semiconductor device, when a contact hole of a high aspect ratio is formed in a fine pattern, it becomes difficult to bury an aluminum alloy film securely in the contact hole.
It is hence a primary object of the invention to present a method of manufacturing a semiconductor device capable of burying a wiring layer such as an aluminum alloy film securely into a contact hole having high aspect ratio.